The invention and discoveries disclosed herein relate to wafer scale integration. In bringing wafer scale devices and complete systems made thereon into commercial reality we have discovered ways to make substantial improvements.
The "chip" is a basis of many of today's advanced computer and electronic devices. However, even as the size of the chip has grown from its original integrated circuit, to a large scale integrated circuit, to a very large scale integrated circuit, these chips have always been manufactured on wafers as an intermediary step in the manufacturing process. The wafer when manufactured is made with many usually identical circuits located in dies spread out across the surface of the wafer. Thereafter these circuits are diced and the individual die become what is referenced to as chips. The reason for dicing is in part based upon the experience that only a few of the circuits which have been built on a wafer end up being good. We think that, until now, pinholes and dust particles have been one of the major problems causing faulty circuits. Pinholes destroy the fine circuit pattern from the mask. In order to get good circuits, the circuits are tested on the wafer then diced and sorted for the individual good chips and then packaged. Often the final high speed tests are only performed after the chip is in its package.
In contrast to this present state of the art, applicants and others had been working on a level of technology which is called "wafer scale integration". This technology utilizes the entire wafer to make a system package, as opposed to a chip package. To understand the technology, gates, diodes, resistors and other well known electrical elements are fundamental units of a circuit, and a circuit is in turn an sub-element of a die, and a die or chip is a sub-element of a wafer. The wafer itself in our version of a monolithic wafer is composed of a plurality of circuits capable of being an entire system or a major subcomponent thereof. This system is of a scale much greater than the systems made on the single chips for the first time approximately a decade ago. Since that time, chips during the last decade have been which have onboard memory, and instruction processors and an interconnection bus to the outside world.
By utilizing available VLSI technology and certain wafer scale integration techniques, dicing techniques can be eliminated. In the past we have made wafer scale devices as disclosed in U.S. Ser. No. 225,581 filed Jan. 16, 1981, which has been abandoned, and its continuation Ser. No. 445,156 filed Nov. 29, 1982, entitled Universal Interconnection Substrate, invented by Stopper et al now U.S. Pat. No. 4,458,297. One of the advantages of this prior art device is that it features electrical programming of chip interconnections. In a nutshell, that means the elimination of the need for custom work or wiring scheme to hook up randomly occurring good chips on each wafer. It is a hybrid technique.
In contrast thereto, personnel at Trilogy have been fabricating ECL circuits in pursuance of the concept of the computer on a chip or wafer. They had expected to package these devices in the year 1984, and the Trilogy approach is different from our approach. Trilogy has announced that they have had substantial technical difficulties and have been unable to prove their technology.
Trilogy has planned on dicing its wafer into larger chips between one inch and two inches square, and packaging those in hermetically sealed, water cooled modules. We are informed that Trilogy has opted to use bumped wafers with area bonding tape. The area bonding tape contacts the wafer bonding pads into a pin grid array with signal lines only on the tape. Power and ground are on a separate distribution network exiting the wafer module on a bus. Trilogy has been utilizing ECL circuits which translate into heat. In dealing with this the use of amorphous calcoginide, the two-way programmable fuse. In Electronics, Sept. 22, 1983, it was reported that our further experimental work utilizes an amorphous "antifuse", which technology employs amorphous silicon. Amorphous, or non-crystalline silicon, serves as an insulator sandwich between two layers of metal on our wafer. Like the prior application, metal lines are laid down in a reticulate array on one or more layers at right angles to another or orthogonally to lines in another layer to permit us to form a programmable via to connect crossing lines.
Because of this connection, a fusing interconnection is caused between the two conductors to connect two lines of a reticulate array together and to permit us to connect chips.
The prior Universal Interconnection Substrate application had means which limited its purposes and this application is directed to an electrically programmable silicon interconnect substrate which can be configured for not only ECL, but also TTL and/or C-MOS or other logic technologies so that, if a hybrid technology is utilized the final array of chips can become a total system on a wafer utilizing various chip technologies. In addition, we have been able to overcome many problems and make the wafer from 100 mm wafers. In a hybrid system, each chip will be bonded to the silicon substrate with epoxy and aluminum wedge or wire bonding. The entire substrate is mounted into a core assembly or module which permits not only air cooled units, but also liquid freon or liquid nitrogen cooling.
The discoveries and inventions we have made in order to accomplish versatile wafer scale systems may be used not only in connection with prior U.S. Pat. No. 4,458,297 previously referenced and incorporated herein fully by reference, but also in systems as disclosed in application U.S. Ser. No. 360,177, filed Mar. 22, 1982 now abandoned, entitled Computer Apparatus and Method, invented by Stopper et al, and also disclosed the above referenced related applications all of which are incorporated fully by reference. A result of the discoveries and inventions we have made will be to permit the assembly of electronics which are faster, smaller and more energy effective and reliable than previous technology. The advantage of the device permits it to utilize TTL circuits, ECL, and/or C-MOS logic with no significant pin out restraint on the integrated circuits themselves. The disclosed wafer system may be 100 mm and permits operation at cold temperatures permitting C-MOS to operate faster. High powered C-MOS devices can achieve bipolar speeds. It is expected that the C-MOS devices will exceed bipolar speeds in the future and our device permits the utilization of C-MOS chips to permit maximum gate counts. The utilization of field programmable interconnection substrates eliminates turnaround and eliminates many masking steps utilized in existing technology and eliminates much of the high capital costs needed for the wafer scale approaches employed by Trilogy. Our improvements permit any available heat sink, such as cool liquid, to be an environment, permitting air or direct immersion liquid cooling to be used with the wafer system. Many technical improvements have been made which have no prior art. The technical improvements are described in the detailed description of the invention and are included in the claims appended hereto.